The present invention relates to a data processor including register banks, more particularly to register set saving and restoring involved in interrupt exception (refers to both interrupts and exceptions) handling and task switching, and a technique effectively applied to, e.g., single chip microcomputers.
When interrupt exception handling or task switching under multitask environments is performed, a predetermined register set such as general purpose registers, a status register, and the like at that time is saved to enable restoration to a previous state. Although a stack area allocated to an external memory and the like can be used as a save destination, register banks can be used to rapidly save and restore the register set. Use of the register bank method shortens interrupt response time.
Patent Publication 1 describes a single-chip microcomputer including general purpose registers of bank structure by use of an internal RAM (random access memory), provided with a dedicated bus for that purpose. Patent Publication 2 describes an information processing unit having a register bank configuration in which a dedicated bus is provided between a register file and an internal RAM. Patent Publication 3 describes an extended central processing unit having a register file configuration with a dedicated bus provided between the register file and an internal RAM.
[Patent Publication 1]
Japanese Unexamined Patent Publication No. Hei 5 (1993)-165641
[Patent Publication 2]
Japanese Unexamined Patent Publication No. Hei 6 (1994)-309169
[Patent Publication 3]
Japanese Unexamined Patent Publication No. Hei 5 (1993)-265753